Present-day data-processing applications perform increasingly complex operations on progressively larger amounts of data. Handling the large amount of data has resulted in memory circuits with increased sophistication and capacity. To reduce the burden and overhead on the processor or processors of interfacing with and controlling the memory, data-processing systems typically include one or more memory controllers.
To address various data storage and retrieval needs, data-processing systems usually include more than one type of memory. Some of the memories use a random-access-memory (RAM) interface to accommodate memory circuits such as dynamic random-access memories (DRAM). Other memories incorporate a chip-select interface (CSI) or chip-enable interface, a typically asynchronous interface that includes address signals, read and/or write enable signals, and a chip-select or chip-enable signal.
Each of those types of memory typically has its own operational specifications which, among other things, include timing and stimulus signal sequences and specifications. Controlling those memory circuits typically entails providing timing and control signals that meet each manufacturer's and each particular part's specifications. To lower costs and reduce physical form factors, RAM devices and CSI devices usually share signal connections and package pins, such as address and data buses.
The sharing of address and data buses usually works well, but refresh operations for synchronous DRAM (SDRAM) devices pose a complication. In a system that includes SDRAM devices, the SDRAM controller (part of the functionality of a memory controller that typically includes a CSI controller) performs refresh operations periodically to avoid dissipation of the charges that represents the data stored within the SDRAM devices. If the system also includes CSI devices, the SDRAM and CSI devices may share address and data buses. In some systems, the SDRAM devices use an interface that includes control signals separate from the CSI devices' control signals. Thus, the refresh operation of the SDRAM devices may proceed without conflict with any transactions with the CSI devices.
In systems that include SDRAM controllers with paging capability, however, the SDRAM controller and the CSI controller may conflict with each other's use of the shared address bus. SDRAM controllers that support paging typically use the same set of control signals that systems without paging use. In addition to those control signals, however, SDRAM controllers that support paging also use an additional signal to ensure proper refresh operations. Memory controllers with paging support commonly use bit 10 of the shared address bus to facilitate closing any open pages before a refresh operation or command issues.
Under normal operating conditions in those systems, the SDRAM controller performs refresh operations at regular intervals. When the time to perform a refresh operation arrives, if the CSI controller is not using the shared address bus, the SDRAM controller may use the shared address bus (e.g., address bit 10) to close any open pages in order to perform refresh operations. If, however, the CSI controller is using the shared address bus and, in particular, address bit 10, the SDRAM controller has to wait until the CSI controller relinquishes the shared address bus.
Conventional systems use techniques such as refresh queues to address and resolve the conflict between the CSI controller's use of the shared address bus and the SDRAM controller's need to use the shared address bus to facilitate refresh operations. Under those circumstances, the SDRAM controller postpones SDRAM refresh operations until the CSI controller relinquishes the shared address bus. The conflict between the CSI controller and the SDRAM controller, however, causes inefficiency and decreased throughput. Moreover, in extreme cases where the CSI controller interfacing with a slow CSI device fails to relinquish the shared address bus for a relatively long time, the SDRAM controller may fail to perform a refresh operation in time to avert loss of data and, possibly, system failure. A need therefore exists for memory controllers that support paging and yet provide a way of performing timely refresh of the SDRAM devices.